ELDQDB-SR: An Enhanced Loop Architecture of DQDB with Slot Reuse

A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an intersegment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alphatuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions. key words: loop, fairness, DQDB, slot reuse